• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
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    • 专利摘要:
    The invention relates to a method of manufacturing an optoelectronic device, comprising: a) reporting, on one side of a control circuit (110), a diode stack (150) comprising first (153) and second (157) ) semiconductor layers of opposite conductivity types, so that the second layer is connected to metal pads (113) of the control circuit; b) forming in the stack of trenches delimiting a plurality of diodes (176) connected to separate metal pads of the control circuit; c) depositing an insulating layer (178, 178 ') on the side walls of the trenches; d) partially removing the insulating layer so as to release the flanks of the portions of the first layer delimited by the trenches; and e) forming a metallization (180) coating the side walls and the bottom of the trenches and contacting the flanks of the portions of the first layer delimited by the trenches.
    公开号:FR3073669A1
    申请号:FR1760578
    申请日:2017-11-10
    公开日:2019-05-17
    发明作者:Hubert Bono；Julia Simon
    申请人:Commissariat a lEnergie Atomique CEA；Thales SA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    METHOD FOR MANUFACTURING AN OPTOELECTRONIC DEVICE COMPRISING A PLURALITY OF DIODES
    Field
    The present application relates to the field of optoelectronic devices. It relates more particularly to a method of manufacturing an optoelectronic device comprising a plurality of semiconductor diodes, for example gallium nitride, and an electronic circuit for controlling these diodes. Presentation of the prior art
    An emissive display device has already been proposed comprising a matrix of light-emitting diodes (LEDs) with gallium nitride (GaN), and a control circuit making it possible to individually control the LEDs to display images.
    To make such a device, provision may be made to manufacture the control circuit and the LED array separately, then to hybridize them, that is to say to stack them by connecting them to each other.
    A drawback of this manufacturing method lies in the need to precisely align the control circuit and the LED array during the step of assembling these two elements, so that each LED comes to be positioned correctly on a metal stud. which corresponds to it in the control circuit. This alignment is particularly difficult to achieve when the pitch
    B16061 - DD17951 - TRT17047 of the pixels decreases, and constitutes a brake with the increase in the resolution and / or the density of integration of the pixels.
    To overcome this drawback, it has been proposed, in particular in international patent application No. PCT / ER2016 / 051140 filed by the applicant on May 13, 2016, to:
    first realize the control circuit in the form of an integrated circuit comprising, on one side, a plurality of metal pads intended to be connected to the LEDs so as to allow the current flowing in each LED to be individually controlled;
    then report on the face of the control circuit comprising the metal studs an active stack of LEDs extending continuously over the entire surface of the control circuit; then structure the active LED stack to delimit and isolate the different LEDs of the device from each other.
    An advantage of this manufacturing process is that, during the step of transferring the active stack of LEDs to the control circuit, the positions of the various LEDs of the device in the active stack are not yet defined. There is therefore no strong constraint in terms of alignment accuracy during the transfer. The delimitation of the various LEDs in the active stack can then be carried out by methods of structuring a substrate and depositing insulating and conductive layers on a substrate, which offer an alignment precision which is clearly greater than the precision which can be obtained during a transfer from one substrate to another.
    However, it would be desirable to at least partially improve certain aspects of the process described in application No. PCT / FR2016 / 051140 mentioned above.
    summary
    Thus, one embodiment provides a method of manufacturing an optoelectronic device, comprising the following steps:
    B16061 - DD17951 - TRT17047
    a) adding, on one face of an integrated control circuit comprising a plurality of metal connection pads, an active diode stack comprising at least first and second doped semiconductor layers of opposite conductivity types, so that the second layer the stack is electrically connected to the metal pads of the control circuit;
    b) forming in the active stack trenches delimiting a plurality of diodes connected to metal studs distinct from the control circuit;
    c) depositing an insulating layer on the side walls of the trenches;
    d) partially removing the insulating layer so as to free the sides of the portions of the first semiconductor layer delimited by the trenches; and
    e) forming a metallization coating the side walls and the bottom of the trenches and contacting the sides of the portions of the first semiconductor layer delimited by the trenches.
    According to one embodiment, the method further comprises, before step a), at least one of the following steps:
    a step of depositing at least a first metal layer over substantially the entire surface of the control circuit on the metal stud side; and a step of depositing at least a second metal layer over substantially the entire surface of the second semiconductor layer opposite the first semiconductor layer.
    According to one embodiment, the formation of the trenches comprises:
    a first step of etching partial trenches crossing the active stack over its entire height and opening onto the upper face of the first or second metal layer; and
    B16061 - DD17951 - TRT17047 a second etching step during which the partial trenches are extended through the first and second metallic layers.
    According to one embodiment, the insulating layer comprises a first part deposited on the sides of the partial trenches, between the first and second etching steps, and a second part deposited on the sides of the trenches after the second etching step.
    According to one embodiment, in step d), the partial removal of the insulating layer is carried out by anisotropic etching.
    According to one embodiment, during the implementation of step a), the active stack is supported by a support substrate located on the side of the first semiconductor layer opposite to the second semiconductor layer, the method further comprising , between step a) and step b), a step of removing the support substrate.
    According to one embodiment, the metallization formed in step e) completely fills the trenches.
    According to one embodiment, the semiconductor diodes are light-emitting diodes.
    According to one embodiment, the diodes are photodiodes.
    According to one embodiment, the first and second semiconductor layers are layers of gallium nitride, the diodes being gallium nitride diodes.
    According to one embodiment, the control circuit is formed in and on a semiconductor substrate.
    Another embodiment provides an optoelectronic device, comprising:
    an integrated control circuit comprising a plurality of metal connection pads;
    on the control circuit, an active diode stack comprising at least first and second doped semiconductor layers of opposite conductivity types, the
    B16061 - DD17951 - TRT17047 second layer of the stack being electrically connected to the metal pads of the control circuit;
    trenches extending in the active stack and delimiting in the active stack a plurality of diodes connected to metal pads separate from the control circuit;
    an insulating layer covering the side walls of the trenches with the exception of at least part of the sides of the portions of the first semiconductor layer delimited by the trenches; and a metallization coating the side walls and the bottom of the trenches and contacting the sides of the portions of the first semiconductor layer delimited by the trenches. Brief description of the drawings
    These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments made without implied limitation in relation to the attached figures, among which:
    Figures IA, IB, IC, 1D, 1E, 1F, IG, IH and II are sectional views illustrating steps of an example of an embodiment of a method of manufacturing an optoelectronic device.
    detailed description
    The same elements have been designated by the same references to the different figures and, moreover, the various figures are not drawn to scale. For the sake of clarity, only the elements which are useful for understanding the embodiments described have been shown and are detailed. In particular, the production of an integrated semiconductor diode control circuit has not been detailed, the embodiments described being compatible with the usual structures and manufacturing methods of such control circuits. In addition, the composition and arrangement of the different layers of an active stack of semiconductor diodes have not been detailed, the embodiments described being compatible with
    B16061 - DD17951 - TRT17047 usual active stacks of semiconductor diodes, in particular with gallium nitride. In the following description, unless otherwise indicated, when referring to qualifiers of absolute position, such as the terms forward, backward, up, down, left, right, etc., or relative, such as the terms above , below, upper, lower, etc., or to orientation qualifiers, such as the terms horizontal, vertical, lateral, etc., reference is made to the orientation of the corresponding figures, it being understood that, in practice , the devices and assemblies described can be oriented differently. Unless specified otherwise, the expressions approximately, substantially, and of the order of mean to 10%, preferably to 5%.
    Figures IA, IB, IC, ID, 1E, 1F, IG, 1H and II are sectional views illustrating steps of an example of an embodiment of a method of manufacturing an optoelectronic device.
    FIG. 1A schematically represents an integrated control circuit 110, previously formed in and on a semiconductor substrate 111, for example a silicon substrate. In this example, the control circuit 110 comprises, on the side of its upper face, for each of the LEDs of the device, a metal connection pad 113 intended to be connected to one of the electrodes (anode or cathode) of the LED, so as to be able to control a current flowing in the LED and / or apply a voltage across the terminals of the LED. The control circuit comprises for example, for each LED, connected to the metal pad 113 dedicated to the LED, an elementary control cell comprising one or more transistors, making it possible to control the current flowing in the LED and / or a voltage applied to the terminals of the LED. The control circuit 110 is for example made of CMOS technology. The metal studs 113 may be laterally surrounded by an insulating material 114, for example silicon oxide, so that the control circuit 110 has a substantially planar upper surface comprising a
    B16061 - DD17951 - TRT17047 alternation (or checkerboard) of metallic regions 113 and insulating regions 114. Contact on the electrodes of LEDs (cathodes or anodes) not connected to the pads 113, can be taken collectively, for example in a region peripheral of the control circuit 110, via one or more connection pads (not visible in the figure) of the control circuit 110.
    FIG. 1A also schematically represents an active stack of gallium nitride LEDs 150, arranged on the upper face of a support substrate 151. The support substrate 151 is for example a substrate made of silicon, sapphire, corundum, or any other material on which an active stack of gallium nitride LEDs can be deposited. In the example shown, the active stack comprises, in order from the upper surface of the substrate 151, a layer of N-type doped gallium nitride 153, an emissive layer 155, and a layer of gallium nitride P-type doped 157. The emissive layer 155 is for example constituted by a stack of one or more emissive layers each forming a quantum well, for example based on GaN, InN, InGaN, AlGaN, AIN, AlInGaN, GaP, AlGaP , AlInGaP, or a combination of one or more of these materials. As a variant, the emissive layer 155 may be a layer of intrinsic gallium nitride, that is to say not intentionally doped, for example with a concentration of residual donors of between 1 (/ 5 and 1 (/ θ atoms / cm ^, for example of the order of 1 (/ ^ atoms / cm / In this example, the lower face of the emissive layer 155 is in contact with the upper face of the layer 153, and the upper face of the emissive layer 155 is in contact with the underside of the layer 157. In practice, depending on the nature of the substrate 151, a stack of one or more buffer layers (not shown) can interface between the support substrate 151 and the nitride layer of gallium 153. The active stack 150 is for example deposited by epitaxy on the support substrate 151.
    FIG. 1B illustrates a step of depositing, on the upper face of the control circuit 110, a metal layer
    B16061 - DD17951 - TRT17047
    116. In the example shown, the metal layer 116 covers substantially the entire upper surface of the control circuit
    110. In particular, the metal layer 116 is in contact with the metal connection pads 113 of the control circuit 110.
    FIG. 1B also illustrates a step of depositing, on the upper face of the active stack of gallium nitride diode 150, with a metal layer 159. In the example shown, the metal layer 159 is placed on and in contact with the upper face of the gallium nitride layer 157. The metal layer 159 for example covers substantially the entire upper surface of the active stack.
    FIG. 1C illustrates a step during which the active stack of gallium nitride LEDs 150 is attached to the upper face of the control circuit 110. For this, the assembly comprising the support substrate 151 and the active stack 150 can be turned over, then added to the control circuit 110, so as to bring the upper face (in the orientation of FIG. 1B) of the metal layer 159 into contact with the upper face of the metal layer 116. During this step, the active stack 150 is fixed (bonded) to the control circuit 110. By way of example, the active stack 150 is fixed to the control circuit 110 can be obtained by molecular bonding between the two surfaces brought into contact. Alternatively, the two surfaces can be fixed by thermocompression, eutectic bonding, or by any other suitable fixing method.
    Once the active LED stack 150 is fixed on the upper face of the control circuit 110, the support substrate 151 of the active LED stack is removed so as to uncover the upper face of the gallium nitride layer 153. The substrate 151 is for example removed by grinding and / or etching from its face opposite the active stack 150. As a variant, in the case of a transparent substrate 151, for example a sapphire or corundum substrate , the substrate 151 can be detached from the active stack 150 by means of a laser beam projected at
    B16061 - DD17951 - TRT17047 through the substrate 151 from its face opposite the active stack 150 (laser lift-off type process). More generally, any other method making it possible to remove the substrate 151 can be used. After the substrate 151 has been removed, an additional etching step may be provided to remove any buffer layers remaining on the side of the upper face of the gallium nitride layer 153. In addition, part of the thickness of the layer of gallium nitride 153 can be removed, for example by etching. At the end of this step, the active stack 150 covers substantially the entire surface of the control circuit 110, without discontinuity. For example, the thickness of the active stack 150 after the withdrawal of the support substrate 151 is between 0.5 and 10 μm.
    FIG. 1D illustrates a step subsequent to the withdrawal of the substrate 151, of depositing a hard mask 171 on the upper face (in the orientation of FIG. 1D) of the active stack of LEDs 150. In this example, the mask hard 171 consists of a stack comprising, in order from the upper face of the gallium nitride layer of type N 157, a first layer of silicon oxide 171a, an intermediate etching stop layer 171b, and a second layer of silicon oxide 171c. The intermediate layer 171b is made of a material that is relatively difficult to etch compared to the silicon oxide, for example aluminum, alumina, or nitride. By way of example, the intermediate layer 171b has a thickness of between 10 and 500 nm, for example of the order of 100 nm.
    FIG. 1D further illustrates a step of forming through openings or trenches 173 in the hard mask 171, for example by photolithography then etching. The trenches 173 extend from the upper face of the hard mask 171 and lead to the upper face of the active LED stack 150. The trenches 173 delimit, in top view, the future individual LEDs 176 of the display device.
    FIG. 1E illustrates a step of extension, through the active stack of LEDs 150, of the trenches 173
    B16061 - DD17951 - TRT17047 previously formed in the hard mask 171. For example, the trenches 173 are extended vertically by etching through the layers 153, 155 and 157 of the LED stack 150, the etching being interrupted on the upper face of the metal layer 159. During this etching step, the upper layer of silicon oxide 171c of the hard mask 171 can be partially or totally consumed. The layers 171b and 171a are however preserved. The extension of the trenches 173 through the active stack 150 leads to delimiting in the active stack 150 a plurality of LEDs with gallium nitride 17 6. Each LED 17 6 corresponds to an island or mesa formed in the stack 150 and surrounded laterally by a trench 173. Thus, each LED 176 comprises a vertical stack comprising, in order from the upper surface of the metal layer 159, a portion of the gallium nitride layer 157, corresponding to the anode of the LED in this example, a portion of the emissive layer 155, and a portion of the gallium nitride layer 153, corresponding to the cathode of the LED in this example. The trenches 173 can be aligned with reference marks previously formed on the control circuit 110. More particularly, in the step of FIG. ID, after the deposition of the hard mask 171 but before the formation of the trenches 173, marks previously formed on the substrate 111 can be released by etching the hard mask 171 and the active stack 150 in peripheral areas of the assembly, these marks then serving as alignment marks for the positioning of the photolithography mask used to produce the trenches 173. In the example shown, each LED 176 is located, in vertical projection, facing a single metal stud 113 of the control circuit 110. In this example, the trenches 173 are located, in vertical projection, facing insulating regions 114 of the upper face of the control circuit 110.
    FIG. 1E also illustrates a step of depositing an insulating layer 178, for example made of silicon oxide, on the
    B16061 - DD17951 - TRT17047 side walls and on the bottom of the trenches 173. In the example shown, the layer 178 is also deposited on the upper face of the portions of the hard mask 171 surmounting the LEDs 176. The layer 178 is for example deposited over the entire upper surface of the device by a conformal deposition method, for example by deposition in successive monoatomic layers (ALD). By way of example, the thickness of the insulating layer 178 is between 10 nm and 1 pm.
    FIG. 1F illustrates a step of removing the insulating layer 178 at the bottom of the trenches 173. During this step, the layer 178 is preserved on the side walls of the trenches 173. For this, the layer 178 is for example etched by anisotropic etching vertical, which also leads to the removal of the layer 178 on the upper face of the portions of the hard mask 171 surmounting the LEDs 176.
    FIG. 1F further illustrates a step of removing, for example by etching, the portions of the metal layers 159 and 116 situated at the bottom of the trenches 173, so as to extend the trenches 173 to the insulating regions 114 of the upper face of the circuit 110. At the end of this step, the anodes (regions 157) of the different LEDs 176 are electrically isolated from each other by the trenches 173, and each LED 176 has its anode connected to the metal stud 113 underlying the intermediate the portions of metal layers 159 and 116 remaining between the LED and the pad 113. This allows individual control of the LEDs by the control circuit 110.
    FIG. IG illustrates a subsequent step of depositing, on the side walls of the trenches 173, a second insulating layer 178 ′, for example made of silicon oxide. The layer 178 ′ is for example deposited on the entire upper surface of the assembly by a conformal deposition technique, then removed only on the upper face of the LEDs 176 and at the bottom of the trenches 173, for example by anisotropic etching.
    FIG. 1H illustrates a subsequent step of removing the insulating layers 178 and 178 ′ on an upper part of the
    B16061 - DD17951 - TRT17047 sidewalls of LEDs 176. More particularly, during this step, the insulating layers 178 and 178 ′ are removed on all or part of the sides of the cathode region 153 of each LED 176, so as to release the access to the sides of cathode region 153 of the LED. By way of example, the insulating layers 178 and 178 'are removed over substantially the entire height of the sides of the cathode regions 153 of the LEDs 176. The layers 178 and 178' are, however, preserved on the sides of a lower part of each LED 176, and in particular over the entire height of the emitting region 155 and of the anode region 157 of each LED 176. In addition, the layer 178 ′ is preserved on the sides of the metal layers 116 and 159. As for example, the removal of layers 178 and 178 ′ on the upper part of the sides of the LEDs 176 is carried out by vertical anisotropic etching. The etching method is preferably chosen so as to selectively etch the silicon oxide with respect to the material of the intermediate layer 171b of the hard mask 171. By way of example, the upper layer of silicon oxide 171c of the hard mask 171 is entirely consumed during this step, while the layer 171b is preserved and makes it possible to protect the lower part 171a of the hard mask 171. The embodiments described are not however limited to this particular case. As a variant, the hard mask 171 can be made entirely of silicon oxide, provided that its thickness is large enough to protect the upper face of the LEDs 176 during the vertical anisotropic etching step of FIG. 1H.
    FIG. II illustrates a subsequent step of depositing a metallization 180 on the side walls and on the bottom of the trenches 173. In the example shown, the metallization 180 completely fills the trenches 173. By way of example, the metallization 180 is carried out by a damascene type process, comprising a step of depositing a metal layer over the entire upper surface of the assembly to a thickness sufficient to fill the trenches 173, followed by a step of mechanochemical polishing of the upper face of the assembly for
    B16061 - DD17951 - TRT17047 planarize the upper face of the device and remove the portions of the metal layer overlying the LEDs 176. In this example, the etching stop layer 171b of the hard mask 171 is also removed during the step of mechanochemical polishing. For example, only the lower silicon oxide layer 171a or part of the thickness of the layer 171a is retained and serves as a passivation layer for the upper face of the cathode regions 153 of the LEDs 176. Metallization 180 is for example made up of a lower bonding layer, comprising for example an aluminum / titanium / titanium nitride / copper stack with a thickness between 10 and 100 nm, for example with a thickness of the order of 50 nm , and an upper filling layer, for example made of copper, deposited by electrochemical deposition. The metallization 180 is in contact with the sides of the cathode region 153 of each LED 176 of the display device, over substantially the entire periphery of the LED. The metallization 180 is however isolated from the sides of the anode regions 157 and the emissive regions 155 of the LEDs by the insulating layers 178 and 178 '. In this example, the metallization 180 forms, in top view, a continuous conductive grid interconnecting the cathode regions 153 of all the LEDs of the device. The metallization 180 is for example connected to the control circuit 110 in a peripheral region of the display device.
    In the embodiment described in relation to FIGS. IA to II, the deposition of the metal layers 116 and 159 on the control circuit 110 and on the active stack 150 (step of FIG. IB) before the postponement of the active stack 150 on the control circuit 110 (step of FIG. IC) has several advantages.
    In particular, layers 116 and 159 make it possible to improve the quality of the bonding between the two structures. Indeed, although possible, direct bonding of the upper face (in the orientation of FIG. IA) of the layer of gallium nitride 157 on the upper surface of the control circuit 110
    B16061 - DD17951 - TRT17047 (comprising an alternation of insulating regions 114 and metal regions 113) is relatively difficult to produce.
    In addition, the layer 159 can advantageously be chosen to make good ohmic contact with the layer of gallium nitride 157. The material of the metal studs 113 of the control circuit 110, for example copper or aluminum, can indeed not be suitable for producing such ohmic contact.
    In addition, the layers 116 and / or 159 may comprise a metal reflecting for the light emitted by the LEDs 176, so as to increase the emission efficiency and avoid loss of light in the control circuit 110.
    Furthermore, the layer 116 and / or the layer 159 can be chosen so as to prevent metal from the connection pads 113 of the control circuit, for example copper, from diffusing towards the gallium nitride layer 157, which could notably degrade the quality of ohmic contact with the layer of gallium nitride 157.
    In practice, each of the layers 116 and 159 may be a single layer or a stack of one or more layers of different metals making it possible to perform all or part of the above-mentioned functions.
    By way of example, the layer 116 comprises an upper layer of a metal of the same kind as an upper layer (in the orientation of FIG. 1B) of the layer 159, this metal being chosen to obtain good bonding between the two structures during the step of FIG. IC, for example a metal from the group comprising Ti, Ni, Pt, Sn, Au, Ag, Al, Pd, W, Pb , Cu, AuSn, TiSn, NiSn or an alloy of all or part of these materials. The stack formed by layers 116 and 159 may further comprise one or more layers of metals suitable for reflecting the light emitted by the LEDs, for example silver. In addition, the stack formed by layers 116 and 159 may comprise one or more layers adapted to act as a barrier to the diffusion of metals such as copper or
    B16061 - DD17951 - TRT17047 the silver included in the stack 116/159 and / or in the metal studs 113, for example layers of TaN, TiN, WN, TiW, or a combination of all or some of these materials .
    Alternatively, layer 116 and / or layer 159 may however be omitted. Preferably, at least one of the layers 116 and 159 is provided, preferably the layer 159 formed on the active stacking side of LED 150.
    An advantage of the process described in relation to FIGS. IA to II is that it has a single photolithography and etching step (to define the location of the trenches 113), which makes it particularly simple and inexpensive to implement.
    Another advantage of this method is that the electrical cathode contact of the LEDs 176 is made laterally over the entire periphery of the cathode regions 153 of the LEDs. This makes it possible to minimize the cathode contact resistance, and thus to limit the electrical consumption of the device.
    Furthermore, the arrangement of cathode contact metallizations 180 in the LED isolation trenches 176 makes it possible to maximize the active surface of the display device. This arrangement also makes it possible to strengthen the optical insulation between the different LEDs 176, and to promote the evacuation of the heat generated by the LEDs 176 in operation.
    It will be noted that in the method described in relation to FIGS. IA to II, the deposition of the layer 178 in the step of FIG. 1E advantageously makes it possible to protect the sides of the active stack of LEDs 150 during the subsequent step of etching the metal layers 159 and 116 in the step of FIG. 1F. As a variant, the deposition of the insulating layer 178 may however be omitted. In this case, only the layer 178 ′ deposited in the step of FIG. IG covers the sides of the LEDs 176 during the step of clearing the sides of the cathode regions 153 of the LEDs illustrated in FIG. IG.
    Particular embodiments have been described. Various variants and modifications will appear to the man of
    B16061 - DD17951 - TRT17047 art. In particular, the types of conductivity of the gallium nitride layers 153 (of type N in the examples described) and 157 (of type P in the examples described) can be reversed.
    Furthermore, although only exemplary embodiments of display devices based on LEDs with gallium nitride have been described, the embodiments described can be adapted to the manufacture of a sensor comprising a plurality of photodiodes at the gallium nitride individually addressable to acquire an image.
    More generally, the embodiments described can be adapted to the manufacture of any display device or photosensitive sensor based on semiconductor diodes, including based on semiconductor materials other than gallium nitride, for example diodes based on other III-V semiconductor materials or silicon-based diodes.
    权利要求:
    Claims (12)
    [1" id="c-fr-0001]
    1. Method for manufacturing an optoelectronic device, comprising the following steps:
    a) add, on one face of an integrated control circuit (110) comprising a plurality of metal pads (113) for connection, an active stack (150) of diode comprising at least first (153) and second (157) doped semiconductor layers of opposite conductivity types, so that the second layer (157) of the stack is electrically connected to the metal pads (113) of the control circuit (110);
    b) forming in the active stack (150) trenches (173) delimiting a plurality of diodes (176) connected to metal pads (113) distinct from the control circuit (110);
    c) depositing an insulating layer (178, 178 ') on the side walls of the trenches (173);
    d) partially removing the insulating layer (178, 178 ') so as to free the sides of the portions of the first semiconductor layer (153) delimited by the trenches; and
    e) forming a metallization (180) coating the side walls and the bottom of the trenches (173) and contacting the sides of the portions of the first semiconductor layer (153) delimited by the trenches.
    [2" id="c-fr-0002]
    2. Method according to claim 1, further comprising, before step a), at least one of the following steps:
    a step of depositing at least a first metal layer (116) over substantially the entire surface of the control circuit (110) on the metal stud side (113); and a step of depositing at least a second metal layer (159) over substantially the entire surface of the second semiconductor layer (157) opposite the first semiconductor layer (153).
    [3" id="c-fr-0003]
    3. Method according to claim 2, in which the formation of the trenches (173) comprises:
    B16061 - DD17951 - TRT17047 a first step of etching partial trenches crossing the active stack (150) over its entire height and opening onto the upper face of the first (116) or second (159) metal layer; and a second etching step during which the partial trenches are extended through the first (116) and second (159) metal layers.
    [4" id="c-fr-0004]
    4. The method of claim 3, wherein the insulating layer (178, 178 ') comprises a first part (178) deposited on the sides of the partial trenches, between the first and second etching steps, and a second part (178' ) deposited on the sides of the trenches (173) after the second etching step.
    [5" id="c-fr-0005]
    5. Method according to any one of claims 1 to 4, wherein, in step d), the partial removal of the insulating layer (178, 178 ') is carried out by anisotropic etching.
    [6" id="c-fr-0006]
    6. Method according to any one of claims 1 to 5, in which, during the implementation of step a), the active stack (150) is supported by a support substrate (151) located on the side from the first semiconductor layer (153) opposite the second semiconductor layer (157), the method further comprising, between step a) and step b), a step of removing the support substrate (151).
    [7" id="c-fr-0007]
    7. Method according to any one of claims 1 to 6, wherein the metallization (180) formed in step e) completely fills the trenches (173).
    [8" id="c-fr-0008]
    8. Method according to any one of claims 1 to 7, in which said semiconductor diodes (176) are light-emitting diodes.
    [9" id="c-fr-0009]
    9. Method according to any one of claims 1 to 7, wherein said diodes are photodiodes.
    [10" id="c-fr-0010]
    10. Method according to any one of claims 1 to 9, in which the first (153) and second (157) semiconductor layers are layers of gallium nitride, said diodes (176) being diodes of gallium nitride.
    B16061 - DD17951 - TRT17047
    [11" id="c-fr-0011]
    11. Method according to any one of claims 1 to 10, in which the control circuit (110) is formed in and on a semiconductor substrate (111).
    [12" id="c-fr-0012]
    12. Optoelectronic device, comprising:
    an integrated control circuit (110) comprising a plurality of metal studs (113) for connection;
    on the control circuit (110), an active diode stack (150) comprising at least first (153) and second (157) doped semiconductor layers of opposite conductivity types, the second layer (157) of the stack being electrically connected to the metal pads (113) of the control circuit (110);
    trenches (173) extending in the active stack (150) and delimiting in the active stack (150) a plurality of diodes (176) connected to metal pads (113) distinct from the control circuit (110);
    an insulating layer (178, 178 ') covering the side walls of the trenches (173) with the exception of at least part of the sides of the portions of the first semiconductor layer (153) delimited by the trenches (173); and a metallization (180) coating the side walls and the bottom of the trenches and contacting the sides of the portions of the first semiconductor layer (153) delimited by the trenches (173).
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    EP3780123A1|2021-02-17|Method for manufacturing optoelectronic devices
    FR3091411A1|2020-07-03|Optimized manufacturing processes of a structure intended to be assembled by hybridization and of a device comprising such a structure
    FR3094568A1|2020-10-02|Manufacturing process of a three-dimensional LED emissive display screen
    FR3111013A1|2021-12-03|Method of manufacturing an optoelectronic device comprising a plurality of diodes
    FR3103634A1|2021-05-28|PROCESS FOR FORMING A COMMON ELECTRODE OF A PLURALITY OF OPTOELECTRONIC DEVICES
    FR3075464A1|2019-06-21|OPTOELECTRONIC DEVICE WITH LIGHT EMITTING DIODES
    同族专利:
    公开号 | 公开日
    US20200335484A1|2020-10-22|
    CN111328430A|2020-06-23|
    KR20200078525A|2020-07-01|
    WO2019092357A1|2019-05-16|
    TW201931587A|2019-08-01|
    EP3707751A1|2020-09-16|
    EP3707751B1|2021-10-20|
    JP2021502699A|2021-01-28|
    FR3073669B1|2021-11-05|
    引用文献:
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    US20150108514A1|2012-11-15|2015-04-23|Xiamen Sanan Optoelectronics Technology Co., Ltd.|Flip-chip light emitting diode and fabrication method|
    US20150333047A1|2012-12-18|2015-11-19|Osram Opto Semiconductors Gmbh|Method for producing optoelectronic semiconductor chips, and optoelectronic semiconductor chip|
    EP3024030A1|2014-11-18|2016-05-25|Commissariat A L'energie Atomique Et Aux Energies Alternatives|Optoelectronic device with light emitting diodes and method of manufacturing the same|
    WO2017037530A1|2015-09-04|2017-03-09|Hong Kong Beida Jade Bird Display Limited|Semiconductor apparatus and method of manufacturing the same|
    WO2017068029A1|2015-10-22|2017-04-27|Commissariat A L'energie Atomique Et Aux Energies Alternatives|Microelectronic diode with optimised active surface|EP3671841A1|2018-12-19|2020-06-24|Commissariat à l'Energie Atomique et aux Energies Alternatives|Method for manufacturing an optoelectronic device comprising a plurality of diodes|
    CN112786762A|2021-01-04|2021-05-11|华灿光电（浙江）有限公司|Light emitting diode epitaxial wafer and preparation method thereof|
    FR3109018A1|2020-04-06|2021-10-08|Commissariat A L'energie Atomique Et Aux Energies Alternatives|DEVICE WITH PHOTO-EMITTING AND / OR PHOTO-RECEIVING DIODES|
    EP3916788A1|2020-05-29|2021-12-01|Commissariat à l'Energie Atomique et aux Energies Alternatives|Method for manufacturing an optoelectronic device comprising a plurality of diodes|
    FR3096508A1|2019-05-21|2020-11-27|Aledia|Light-emitting diode optoelectronic device|
    JP2020202351A|2019-06-13|2020-12-17|日亜化学工業株式会社|Manufacturing method of light emitting element|
    FR3099966B1|2019-08-16|2021-09-24|Commissariat Energie Atomique|Manufacturing process of optoelectronic devices|
    FR3103634B1|2019-11-21|2021-12-03|Commissariat Energie Atomique|PROCESS FOR FORMING A COMMON ELECTRODE OF A PLURALITY OF OPTOELECTRONIC DEVICES|
    法律状态:
    2019-05-17| PLSC| Publication of the preliminary search report|Effective date: 20190517 |
    2019-11-29| PLFP| Fee payment|Year of fee payment: 3 |
    2020-11-30| PLFP| Fee payment|Year of fee payment: 4 |
    2021-11-30| PLFP| Fee payment|Year of fee payment: 5 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1760578A|FR3073669B1|2017-11-10|2017-11-10|METHOD OF MANUFACTURING AN OPTOELECTRONIC DEVICE INCLUDING A PLURALITY OF DIODES|
    FR1760578|2017-11-10|FR1760578A| FR3073669B1|2017-11-10|2017-11-10|METHOD OF MANUFACTURING AN OPTOELECTRONIC DEVICE INCLUDING A PLURALITY OF DIODES|
    TW107138510A| TW201931587A|2017-11-10|2018-10-31|Method of manufacturing an optoelectronic device comprising a plurality of diodes|
    PCT/FR2018/052742| WO2019092357A1|2017-11-10|2018-11-06|Process for fabrication of an optoelectronic device comprising a plurality of diodes|
    KR1020207013027A| KR20200078525A|2017-11-10|2018-11-06|Method for manufacturing an optoelectronic device having a plurality of diodes|
    US16/762,090| US20200335484A1|2017-11-10|2018-11-06|Process for fabrication of an optoelectronic device comprising a plurality of diodes|
    CN201880072922.XA| CN111328430A|2017-11-10|2018-11-06|Method for manufacturing an optoelectronic device comprising a plurality of diodes|
    EP18812238.6A| EP3707751B1|2017-11-10|2018-11-06|Manufacturing process of an optoelectronic device comprising a plurality of diodes|
    JP2020524849A| JP2021502699A|2017-11-10|2018-11-06|How to manufacture optoelectronic devices with multiple diodes|
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